1. Field of the Invention
The invention relates to a field effect transistor (FET) and a method of fabricating the same, and more particularly to a field effect transistor having a gate electrode oriented along a specific direction, and a method of fabricating the same.
2. Description of the Prior Art
As illustrated in FIG. 1, a conventional field effect transistor (hereinafter, referred to simply as xe2x80x9cFETxe2x80x9d) comprises a semi-insulating GaAs substrate 1, a non-doped GaAs layer 2 formed on the substrate 1, an n type GaAs layer 3 formed on the non-doped GaAs layer 2 with a thickness of about 200 nm and a dose of about 2.0xc3x971017 cmxe2x88x923 impurities, and an n+ GaAs layer 5 is formed on the n type GaAs layer 3 with a thickness of about 100 nm and a higher dose than the n type GaAs layer 3, which is about 1.0xc3x971018 cmxe2x88x923. These epitaxial layers are grown by molecular beam epitaxy (MBE).
Then, the n+ type GaAs layer 5 and the n type GaAs layer 3 are selectively wet-etched to thereby form a recess therein in order to enhance break down voltage of FET. On a surface of the n type GaAs layer 3 constituting a bottom surface of the recess is formed a gate electrode 6 made of material such as WSi making Schottky-junction, and on the n+ type GaAs layer 5 are formed a source electrode 7 and a drain electrode 8 both made of an AuGe/Ni film and both making an ohmic junction. Exposed surfaces of these layers 3 and 5, the source and drain electrodes 7 and 8, and the gate electrode 6 are covered with a passivation film 9 made of material such as silicon dioxide.
FIG. 2 illustrates crystal orientation of a semi-insulating GaAs substrate. As illustrated, the gate electrode 6 is formed so that it is oriented with respect to a gate width-wise direction in crystal orientation [01(xe2x88x921)]. Herein, xe2x80x9c(xe2x88x921)xe2x80x9d means a negative direction in Z-axis. The reason why the crystal orientation [01(xe2x88x921)] is selected is as follows. It is known in the art that a silicon dioxide film formed on a GaAs layer in general formation conditions has compressive stress of about 1xc3x97109 dyne/cm2. Thus, the passivation film 9 made of silicon dioxide and formed on the n type GaAs layer 3 induces compressive stress in GaAs crystal in the neighborhood of the gate electrode 6 to thereby induce piezoelectric charge, as having been reported in IEEE Transactions on electron devices, Vol. ED-31, No. 10, October 1984, pp. 1377-1380. The piezoelectric charge is fixed charge and has crystal orientation dependency. In particular, fixed charges to be induced in [01(xe2x88x921)] and [011] orientations have common absolute values, but have opposite signs. It is also known in the art that the fixed charge causes transfer conductance to be varied. Accordingly, a conventional FET is designed to have [01(xe2x88x921)] orientation so that transfer conductance thereof is maximized.
As an alternative, a doping profile of an active layer may be changed in order to enhance linearity of transfer conductance. FIG. 3 illustrates an example of a conventional FET including an active layer doping profile of which is changed.
The illustrated FET includes a semi-insulating GaAs substrate 1, a non-doped GaAs layer 2 formed on the substrate 1, an n type GaAs layer 3 formed on the non-doped GaAs layer 2 with a thickness of about 100 nm at and a dose of about 3.0xc3x971017 cmxe2x88x923 impurities, an nxe2x88x92 type GaAs layer 4 which is formed on the n type GaAs layer 3 with a thickness of about 150 nm and a dose of about 5.0xc3x971016 cmxe2x88x923 impurities and which is formed with a recess, an n+ GaAs layer 5 formed on the nxe2x88x92 type GaAs layer 4, a gate electrode 6 formed in the recess formed in the nxe2x88x92 type GaAs layer 4, a source electrode 7 and a drain electrode 8 both formed on the n+ GaAs layer 5 so that the gate electrode 6 is disposed therebetween, and a silicon dioxide passivation film 9 covering exposed surfaces of the layers 4 and 5, the gate electrode 6, and the source and drain electrodes 7 and 8 therewith. Since the semiconductor active layer 4 disposed just beneath the gate electrode 6 is formed in a stepped structure, the linearity in transfer characteristic is enhanced, as has been reported in IEEE Transactions on Electron Devices, Vol. ED-25, No. 6, June 1978, pp. 600-605.
The firstly mentioned conventional FET has a problem in that the compressive stress induced in a passivation film induces piezoelectric charge in the vicinity of a gate electrode to thereby degrade the linearity and hence the strain characteristic of transfer conductance. Even if the doping profile of an active layer is shaped in a stepped structure, it is not possible to have sufficient linearity of transfer conductance, as has been explained in connection with the secondly mentioned conventional FET illustrated in FIG. 3.
In view of the foregoing problems of the conventional FETs, it is an object of the present invention to provide a field effect transistor which can enhance the linearity and hence strain characteristic of transfer conductance.
In one aspect, the present invention provides a field effect transistor including (a) a semi-insulating GaAs substrate, (b) a step-doped structured active layer including an n type GaAs layer formed on the substrate, and an nxe2x88x92 type GaAs layer or a non-doped GaAs layer formed on the n type GaAs layer, the nxe2x88x92 type GaAs layer or non-doped GaAs layer being formed with at least one recess, and (c) a gate electrode formed in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation [01(xe2x88x921)].
The present invention provides a field effect transistor including (a) a semi-insulating GaAs substrate, (b) an n type GaAs layer deposited on the substrate, (c) an nxe2x88x92 type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, the nxe2x88x92 type GaAs layer or non-doped GaAs layer being formed with at least one recess extending along crystal orientation [011], and (d) a gate electrode formed in the recess so that gate electrode orientation thereof is [011].
The present invention provides a field effect transistor including (a) a semi-insulating GaAs substrate, (b) an n type GaAs layer deposited on the substrate, (c) an nxe2x88x92 type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, (d) an n+ type GaAs layer deposited on the nxe2x88x92 type GaAs layer or non-doped GaAs layer, a first recess being formed so that the first recess passes through the n+ type GaAs layer and terminates in the nxe2x88x92 type GaAs layer or non-doped GaAs layer, a second recess being formed at a bottom surface of the first recess, both the first and second recesses extending along crystal orientation [011], (e) a gate electrode formed in the second recess, (f) source and drain electrodes disposed on the n+ type GaAs layer so that the gate electrode is located therebetween, and (g) a passivation film covering exposed surfaces of a resultant.
In another aspect, the present invention provides a method of fabricating a field effect transistor including the steps of (a) preparing a semi-insulating GaAs substrate, (b) forming a step-doped structured active layer including an n type GaAs layer deposited on the substrate, and an nxe2x88x92 type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, (c) forming the nxe2x88x92 type GaAs layer or non-doped GaAs layer with at least one recess, and (d) forming a gate electrode in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation [01(xe2x88x921)].
The present invention further provides a method of fabricating a field effect transistor including the steps of (a) preparing a semi-insulating GaAs substrate, (b) depositing an n type GaAs layer on the substrate, (c) depositing an nxe2x88x92 type GaAs layer or a non-doped GaAs layer on the n type GaAs layer, (d) forming at least one recess at a surface of the nxe2x88x92 type GaAs layer or non-doped GaAs layer so that the recess extends along crystal orientation [011], and (e) forming a gate electrode in the recess.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.